1. Field of the Invention
This invention relates to a dynamic random access memory (hereinafter, abbreviated as DRAM) cell structure of a one-transistor and capacitor type and a manufacturing method thereof. More specifically, this invention relates to a DRAM cell structure suitable for obtaining a memory capacity equal to or more than 4 Mbits. The present invention is intended to reduce a cell area, simplify fabrication processes by minimizing a number of necessary mask steps and increase reliability through better isolation between adjacent cells.
2. Description of the Related Art
With increasing memory capacity, a cell structure of the DRAM device has a tendency to adopt a three-dimensional form rather than a planar form. For example, a device having one-transistor and a capacitor formed vertically in a deep trench is disclosed at IEDM 85 (1985 IEEE International Electron Device Meeting): "A trench transistor cross-point DRAM cell" by W. F. Richardson et al. IEDM Tech. Dig. 1985, pp. 714-717.
FIG. 1(a) is a top view of the cell layout and FIG. 1(b), a cross section of the DRAM cell disclosed above. A p-type epitaxial layer 2 is grown on a p.sup.+ -type substrate 1. A recessed oxide isolation 3 and n.sup.+ -type diffusion region 9 are formed around a trench 4. Diffusion region 9 functions as a drain of the vertically formed NMOS transistor 51 and the drain is mutually connected with adjacent drains arranged in the Y-direction of rectangular coordinates, forming a bit line. After forming the trench 4, a capacitor dielectric film 5 is formed on an inner wall of the trench and the trench is filled with phosphorous doped polysilicon. The doped polysilicon is etched back leaving a storage electrode 6.
A trench wall around the top of the storage electrode 6 is partially etched and removed, and a buried lateral contact 10 of polysilicon is deposited therein. The buried lateral contact 10 is later subjected to a thermal diffusion of phosphorous impurities from the storage electrode 6 and serves as a source of the vertical NMOS transistor 51. Thereafter, a gate oxide film 8 is formed by thermal oxidation on an inner cylindrical wall of the trench. A thicker oxide layer 50 is formed on the top of the storage electrode 6 by the thermal oxidation process. Finally, a word line 11, which functions as a gate of the NMOS transistor 51, is formed by depositing and patterning the phosphorous doped polysilicon or aluminum alloy.
In FIG. 1(b), a capacitor is composed of the storage electrode 6 and the surrounding substrate portion thereof. The dielectric film 5 is sandwiched therebetween. The above substrate portion surrounding the trench is used as the common capacitor electrode for all cells and is called a cell plate 7.
When an information bit is input through the bit line 9 to a specific cell which is addressed by the word line 11, the NMOS transistor 51 becomes conductive and electric charges are stored in the capacitor. The structure of FIGS. 1(a) and 1(b) utilizes a capacitor which is formed deep in the trench below the transistor. Therefore, the effective capacitance of the memory cell can be easily increased with increasing depth of the trench within a limited cell area, resulting in a high integration density DRAM.
However, the above structure has problems such that the recessed oxide isolation 3 requires a specified distance between neighboring diffusion regions 9, thus limiting an achievable minimum gap distance between cells. Further, if a short gap between cells is selected, a punch-through phenomenon between diffusion regions 9 (drain) may occur, thus resulting in a memory failure or information error.
An improved structure for a DRAM is disclosed by K. Minegishi, T. Morie, and et al in Japan Unexamined Patent Publication SHO-63-66963 dated Mar. 25, 1988. FIG. 2 herein shows a schematic perspective view of the structure of the Minegishi et al. type DRAM, wherein two sectional views in two directions are illustrated taken along the X-axis and Y-axis. The vertical NMOS transistor 62 is formed in an isled pillar region 64 on a p-type substrate 60. The pillar region is surrounded by insulating layers 65 and 66. The NMOS transistor 62 comprises an n.sup.+ -type drain 67, and an n.sup.+ -type source occupying a top portion of an n.sup.+ -type epitaxial layer 68. A gate electrode 63 is formed outside the isled pillar region 64 insulated by a gate insulating layer 65, and functions as a word line. In FIG. 2, a bit line, formed on a top of the isled region 64 and connecting plural drains 67 in the X-direction, has been omitted. A capacitor is composed of the n.sup.+ -type epitaxial layer 68 (called a storage electrode), a doped polysilicon 69 (called a cell plate), and the insulating layer 66 sandwiched therebetween.
As seen in FIG. 2, a p.sup.+ -type isolation region 70 is required which is formed by boron ion implantation in a p-type substrate 60. The isolation region 70 should be formed at the lower portion of the trench before it is buried with the doped polysilicon 69. A high impurity concentration is required for the isolation region 70 to eliminate leakage of electric charges between adjacent storage electrodes 68. This is due to the fact that the cell plate (doped polysilicon 69) easily induces an inversion layer on an opposite bottom surface of the insulating layer 66.
The above DRAM structure has a problem in that a level of the lower surface 71 of the gate electrode 63 should be formed substantially equal to an interface level between the n.sup.+ epitaxial layer 68 and p-type epitaxial layer 73 where the channel region and drain 67 of NMOS transistor 62 are formed.
Due to the above two factors, i.e., formation of the isolation region 70 and level matching, the fabrication of this type of DRAM is relatively difficult. Also, a sufficient degree of reliability is difficult to obtain.